A conventional module is described with reference to FIGS. 19A and 19B.
FIGS. 19A and 19B are sectional views of a conventional module. In FIGS. 19A and 19B, conventional module 1 includes circuit board 4, components 6 such as a semiconductor chip, a laminated ceramic capacitor, and a square chip resistor mounted on circuit board 4, and sealing part 3 made of an epoxy resin for sealing thereof. Furthermore, metal film 2 of a metal paste and the like is formed thereon.
Circuit board 4 includes wiring (not shown) including a copper foil pattern provided on a surface layer or an inner layer thereof, ground layer 5 including a copper foil pattern for shielding, and epoxy layer 7 for connecting thereof. Epoxy layer 7 is an interlayer insulating layer formed by impregnating glass woven fabric and the like with an epoxy resin.
In FIGS. 19A and 19B, metal film 2 is provided for shielding, and connected to epoxy layer 7 and ground layer 5 exposed to the wall surface thereof, which constitute circuit board 4.
In FIG. 19B, peeled portion 8 occurs in the vicinity of a connection portion between metal film 2 and ground layer 5. Peeled portion 8 is a peeled portion (which is also referred to as a “void portion”) occurring in an interface portion between epoxy layer 7 and ground layer 5 when circuit board 4 is cut. Since peeled portion 8 looks white in observation under a microscope and the like, it may be also referred to as a whitened part.
FIG. 20 is a side view illustrating a peeled portion of a conventional module. The peeled portion is described in detail with reference to FIG. 20. FIG. 20 corresponds to a side view of module 1 before metal film 2 made of conductive paste and the like is formed on a surface thereof.
As shown in FIG. 20, it is shown that peeled portions 8a and 8b occur in the interface between ground layer 5 exposed to the side surface of circuit board 4 and epoxy layer 7 that is brought into contact with ground layer 5.
Such peeled portions 8a and 8b easily occur on a cut surface of circuit board 4 when one circuit board 4 is divided into a plurality of units by, for example, dicing.
Circuit board 4 in which such peeled portions 8a and 8b occur may affect reliability. Even if metal film 2 is provided on peeled portions 8a and 8b once occurred, it is difficult to bond again the interface between epoxy layer 7 and ground layer 5 which are once separated. Since FIG. 20 shows a state before metal film 2 is formed, metal film 2 is not shown.
When a sealing structure (not shown) provided by mounting a plurality of components 6 on one large circuit board and sealing it with sealing part 3 is divided into a plurality of pieces by, for example, dicing so as to form module component 1, peeled portions 8a and 8b easily occur. This is because when separate members, that is, sealing part 3 and circuit board 4, are divided and cut simultaneously, a stress easily concentrates on peeled portions 8a and 8b. That is to say, in conventional circuit board 4, when ground layer 5 is exposed to an end surface (or a cut surface) of circuit board 4, interfacial peeling such as peeled portion 8 may occur in the interface between ground layer 5 and epoxy layer 7 adjacent to ground layer 5.
As the prior art document regarding this invention, the following Patent Literature 1 is known.